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| 500mA SmartLDO With Power Up Signal Sequencing PRELIMINARY - January 17, 2000 TM SC1545 TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com DESCRIPTION The SC1545 was designed for instantly available motherboard applications. As part of the Semtech family of SmartLDO's it provides additional control functions not available in a standard LDO. The device provides the capability to control three separate supplies. There is an on-board 500mA, 2.5V LDO with current limit protection, and drive pins for an N-channel MOSFET and a P-channel MOSFET. Internal logic circuitry ensures that the system starts up in a controlled manner, and that the correct outputs are enabled during specific sequences of BF_CUT and SLP. The LDO draws its power from the 5V standby supply, and the N-channel MOSFET drive is derived from the 12V supply. The SC1545 is available in the surface mount SO-8 package. FEATURES * * * 500mA LDO with Over Current Protection (OCP) 2.5% LDO regulation over line, load and temperature Power sequencing for three supplies APPLICATIONS * * * Instantly available motherboards Embedded systems Desktop computers ORDERING INFORMATION Part Number SC1545CS (1) Package SO-8 Note: (1) Add suffix `TR' for tape and reel packaging. TYPICAL APPLICATION CIRCUIT 2.5V IN Q1 2.5V OUT Si4410 C1 2 x 100uF C2 100uF 3.3V IN Q2 3.3V OUT IRLMS6802 C3 2 x 100uF C4 100uF U1 1 2.5V OUT 2 3 4 C5 10uF VO GND PDR NDR SC1545 5VSTBY 12VIN BF_CUT SLP 8 7 6 5 C6 1uF C7 0.1uF 5V STANDBY 12V IN BF_CUT SLP 1 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 500mA SmartLDO With Power Up Signal Sequencing PRELIMINARY - January 17, 2000 TM SC1545 ABSOLUTE MAXIMUM RATINGS Parameter 12V Input Voltage Range 5V Input Voltage Range P-channel MOSFET Gate Drive N-channel MOSFET Gate Drive Input Pins Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec Thermal Impedance Junction to Case Thermal Impedance Junction to Ambient ESD Rating Note: (1) 2 inch square of 1/16" FR-4, double sided, 1 oz. minimum copper weight. (1) Symbol 12VIN 5VSTBY PDR NDR Maximum -0.3 to +15 -0.3 to +7 -0.3 to 5VSTBY -0.3 to 12VIN -0.3 to +7 Units V V V V V C C C C C/W C/W kV TA TJ TSTG TLEAD JC JA ESD 0 to +70 0 to +125 -65 to +150 300 47 65 2 ELECTRICAL CHARACTERISTICS Unless specified, 12VIN = 12V, 5VSTBY = 5V, CO = 100F min., TA = 25C. Values in bold apply over full operating temperature range. Parameter 12VIN Supply Voltage Quiescent Current Symbol Test Conditions MIN TYP MAX Units 12VIN IQ12 11.28 12.00 12.72 800 1000 1200 V A 5VSTBY Supply Voltage Quiescent Current 5VSTBY IQ5 LDO ON 4.7 5.0 9.5 5.3 11 12 LDO OFF 3.0 4.0 5.0 Undervoltage Lockout (5V) UVLO Threshold UVLO 5VSTBY rising 5VSTBY falling Hysteresis Logic Reset Threshold HYST RST 1.5 4.1 3.9 4.3 4.1 200 2.0 2.5 4.5 4.3 V V mV V mA V 2 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 500mA SmartLDO With Power Up Signal Sequencing PRELIMINARY - January 17, 2000 TM SC1545 ELECTRICAL CHARACTERISTICS (Cont.) Unless specified, 12VIN = 12V, 5VSTBY = 5V, CO = 100F min., TA = 25C. Values in bold apply over full operating temperature range. Parameter VO LDO Output Voltage Symbol Test Conditions 4.7V 5VSTBY 5.3V, 1mA IO 500mA MIN TYP MAX Units VO -1.5% 2.525 +1.5% -2.5% +2.5% V LDO Output Voltage During (1) Load Transients Time To Regulation (2) VO(T) tREG RIN VIH VIL INDR(PK) VNDR tDL(N) tf(N) tDH(N) tr(N) IPDR(PK) VPDR tDL(P) tf(P) tDH(P) tr(P) ICL Load step between 0mA and 500mA at 8A/s max. -3.0% 2.525 +3.0% 5 V s Inputs (BF_CUT & SLP) Input Resistance High Level Input Voltage Low Level Input Voltage NDR Peak Drive Current Output Voltage Drive Low Delay Fall Time Drive High Delay Rise Time PDR Peak Drive Current Output Voltage Drive Low Delay Fall Time Drive High Delay Rise Time Overcurrent Protection Current Limit Threshold VO = 0V 550 mA Sinking: PDR = 0.5V Sourcing: PDR = 3.5V Full ON, IPDR = 100A Measured from BF_CUT threshold to 90% of PDR Measured from 90% to 10% Measured from BF_CUT/SLP threshold to 10% of PDR Measured from 10% to 90% 30 3.5 5 150 1.0 300 1.0 mA V ns s ns s Sinking: NDR = 0.5V Sourcing: NDR = 10V Full ON, INDR = 100A Measured from BF_CUT threshold to 90% of NDR Measured from 90% to 10% Measured from BF_CUT/SLP threshold to 10% of NDR Measured from 10% to 90% 30 10 12 150 1.0 300 1.0 mA V ns s ns s BF_CUT = SLP = 5V 1.0 2.0 0.8 10.0 M V V NOTES: (1) The LDO will bring the output back to within the regular VO limits in less than 10s. (2) External 2.5V 2.5% applied at output, turning off when NDR goes low. CO = 100F to 400F, IO = 50mA to 200mA. 3 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 500mA SmartLDO With Power Up Signal Sequencing PRELIMINARY - January 17, 2000 TM SC1545 BLOCK DIAGRAM PIN CONFIGURATION Top View PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 Pin Name Pin Function VO GND PDR NDR SLP LDO 2.5V output. Logic and power ground. Gate drive signal for P-channel MOSFETs. Gate drive signal for N-channel MOSFETs. Control input #1. BF_CUT Control input #2. 12VIN +12V input supply. Used for generating NDR only. 5VSTBY +5V input supply. SOIC-8 4 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 500mA SmartLDO With Power Up Signal Sequencing PRELIMINARY - January 17, 2000 TM SC1545 TYPICAL CHARACTERISTICS 12VIN Quiescent Current vs. Junction Temperature 1000 12VIN = 12V 900 800 700 IQ12 (A) 600 500 400 300 200 100 0 0 25 50 TJ (C) 75 100 125 IQ5(ON) (mA) 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 0 25 50 TJ (C) 75 100 125 10.0 5VSTBY = 5V 5VSTBY Quiescent Current (ON) vs. Junction Temperature 5VSTBY Quiescent Current (OFF) vs. Junction Temperature 5.0 5VSTBY = 5V 4.5 4.0 3.5 IQ5(OFF) (mA) UVLO (V) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 25 50 TJ (C) 75 100 125 4.5 4.4 4.4 4.3 4.3 4.2 4.2 4.1 4.1 4.0 0 4.5 5VSTBY Under Voltage Lockout vs. Junction Temperature 5VSTBY RISING 5VSTBY FALLING 25 50 TJ (C) 75 100 125 LDO Output Voltage vs. Junction Temperature 2.550 5VSTBY = 5V 2.545 2.540 2.535 2.530 VO (V) 2.525 2.520 2.515 2.510 2.505 2.500 0 25 50 TJ (C) 75 100 125 IO = 500mA REGLINE (mV) IO = 1mA 9 8 7 6 5 4 3 2 1 0 0 25 10 LDO Line Regulation vs. Junction Temperature 5VSTBY = 4.7V to 5.3V 50 TJ (C) 75 100 125 5 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 500mA SmartLDO With Power Up Signal Sequencing PRELIMINARY - January 17, 2000 TM SC1545 TYPICAL CHARACTERISTICS (Cont.) VDO Current Limit vs. Junction Temperature 1000 900 800 700 ICL (mA) 600 500 400 300 200 100 0 0 25 50 TJ (C) 75 100 125 VO = 0V TIMING DIAGRAMS Power up signal sequencing is shown in Figure 1. BF_CUT, PDR and NDR follow the power rails up to their final values. SLP goes to its high value when the power rails have stabilized, ~25msec after power on. BF_CUT is pulled low a period T1 after SLP goes high. T1 can be as short as 1msec. Typical measured values are ~200msec. The 2.5V LDO output stays OFF through this sequence. Figure 1: Power Up Signal Sequencing 6 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 500mA SmartLDO With Power Up Signal Sequencing PRELIMINARY - January 17, 2000 TM SC1545 TIMING DIAGRAMS (Cont.) After power up, there are two possible signal sequences that the device will see. The first sequence is with SLP staying HIGH and BF_CUT transitioning from LOW to HIGH, remaining HIGH for an undetermined period and then going back to LOW. At this point, the system state is back to where it was at the end of the power up sequence. The sequence is shown in Figure 2 (below). During these BF_CUT transitions, the propagation delays, rise and fall times and going into regulation times for PDR, NDR and VO are described in Electrical Characteristics on page 3. The first sequence can start at any time after the end of the power up sequence. Figure 2: 1st Sequence Timing Signal sequencing for the second possible sequence is shown in Figure 3. BF_CUT goes from LOW to HIGH and SLP goes from HIGH to LOW, 30sec to 65sec (T3) later. When BF_CUT goes HIGH, PDR and NDR go LOW and the 2.5V LDO turns ON. When SLP goes LOW, PDR and NDR return to HIGH and the 2.5V LDO turns OFF. BF_CUT will stay HIGH and SLP will stay low for an undetermined time, after which SLP will go HIGH. A minimum of 1msec (T4) later, BF_CUT will go LOW and the system is back at the end of the power up sequence. Typical measured values of T4 are ~250msec. During all transitions, the propagation delays, rise and fall times, and going into regulation times for PDR, NDR and 2.5V LDO are described in Electrical Characteristics on page 3. The second sequence can start at any time after the end of the power up sequence. Figure 3: 2nd Sequence Timing 7 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 500mA SmartLDO With Power Up Signal Sequencing PRELIMINARY - January 17, 2000 TM SC1545 OUTLINE DRAWING JEDEC REF: MS-012AA MINIMUM LAND PATTERN - SO-8 ECN99-694 ECN00-831 8 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 |
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